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ds05-30333-1e fujitsu semiconductor data sheet memory 5v-only flash memory card MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 1m/2m/4m/8m/16m/32m-byte 5v-only flash erasable and programmable memory card n description the fujitsu 5v-only flash memory cards are electrically erasable and programmable memory cards capable of storing and retrieving large amounts of data. the memory circuits are housed in a credit-card sized 68-pin package. internal circuit is protected by two metal panels, one at the top and the other at the bottom of the card, that help to reduce chip damage from electrostatic discharge. a unique feature of the fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus con?uration. all cards are portable and operate on low power at high speed. in accordance with the personal computer memory card internal association (pcmcia) and japan electrical industry development association (jeida) industry standard speci?ations, flash memory cards offer additional eeprom memory that is used to store attribute data. the attribute memory is a flash memory card option. (see page 3 for description of the three available options.) n absolute maximum ratings (*1) *1: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional oper- ation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit supply voltage v cc ?.5 to +6.0 v input voltage v in ?.5 to v cc +0.5 v output voltage v out ?.5 to v cc +0.5 v temperature under bias t a 0 to +60 c storage tmperature t stg ?0 to +70 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n product line & features meet pcmcia and jeida industry standards for 68-pin memory card credit card size : 85.6 mm (length) 54.0 mm (width) 3.3 mm (thickness) +5 v 5% power supply program and erase command control for automated program / automated erase operation erase suspend read / program capability (only erase suspend read is possible for MB98A81063) 128 kb sector erase (at 16 mode) any combination of sectors erase and full chip erase detection of completion of program/erase operation with data polling or toggle bit. ready/busy output with r/b (except for MB98A81063) reset function with reset pin (except for MB98A81063) write protect function with wp switch ?ow v cc write inhibit n package crd-68p-m05
3 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n descriptions description table differences part number common memory attribute memory memory device organization (w bit) access time memory device organiza- tion (w bit) access time MB98A81063 4m bit flash memory 2 1m 8/512k 16 max 150 ns 16k bit eeprom 1 2k 8 max 250 ns mb98a81183 8m bit flash memory 2 2m 8/1m 16 mb98a81273 16m bit flash memory 2 4m 8/2m 16 mb98a81373 16m bit flash memory 4 8m 8/4m 16 mb98a81473 16m bit flash memory 8 16m 8/8m 16 mb98a81573 16m bit flash memory 16 32m 8/16m 16 mb98a8106 3 mb98a8118 3 mb98a8127 3 mb98a8137 3 mb98a8147 3 mb98a8157 3 density 1mb 2mb 4mb 8mb 16mb 32mb memory device 4m bit 8m bit 16m bit ??? quantity 22248 16 read 1 b unit ????? program 1 b unit ????? chip erase 512 kb unit 1 mb unit 2 mb unit ??? sector erase 64 kb unit ????? number of sectors 16 32 64 128 256 512 erase suspend read yes yes yes yes yes yes erase suspend program no yes yes yes yes yes address a 0 to a 19 a 0 to a 20 a 0 to a 21 a 0 to a 22 a 0 to a 23 a 0 to a 24 reset no yes yes yes yes yes r/b no yes yes yes yes yes
4 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n descriptions (continued) address map (for x 16 mode, not contained a 0 ) chip15,14 chip13,12 chip11,10 chip9,8 chip7,6 chip5,4 chip3,2 chip1,0 chip7,6 chip5,4 chip3,2 chip1,0 chip3,2 chip1,0 chip1,0 chip1,0 chip1,0 MB98A81063 mb98a81183 mb98a81273 mb98a81373 mb98a81473 mb98a81573 ffffffh dfffffh bfffffh 9fffffh 7fffffh 5fffffh 3fffffh 1fffffh 0fffffh 07ffffh 000000h
5 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n pin assignments * : see ?escriptions? pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1 gnd 18 nc. 35 gnd 52 nc. 2d 3 19 a 16 36 cd 153a 22 /nc.* 3d 4 20 a 15 37 d 11 54 a 23 /nc.* 4d 5 21 a 12 38 d 12 55 a 24 /nc.* 5d 6 22 a 7 39 d 13 56 nc. 6d 7 23 a 6 40 d 14 57 nc. 7ce 124 a 5 41 d 15 58 reset/nc. 8a 10 25 a 4 42 ce 2 59 nc. 9oe 26 a 3 43 nc. 60 nc. 10 a 11 27 a 2 44 nc. 61 reg 11 a 12 28 a 1 45 nc. 62 bvd2 12 a 12 29 a 0 46 a 17 63 bvd1 13 a 13 30 d 0 47 a 18 64 d 8 14 a 14 31 d 1 48 a 19 65 d 9 15 we 32 d 2 49 a 20 /nc.* 66 d 10 16 r/b /nc.* 33 wp 50 a 21 /nc.* 67 cd 2 17 v cc 34 gnd 51 v cc 68 gnd
6 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n pin descriptions n pin locations symbol pin name input/output function a 0 to a 24 address input input address inputs, a 0 to a 24 . d 0 to d 15 data input/output input/output data inputs/outputs. this data bus size (8-bit or 16-bit) is selected with ce 1 and ce 2. ce 1 card enable for lower byte input active low. -lower byte (d 0 to d 7 ) is selected for read/write/ erase function of ?sh memory cards. ce 2 card enable for upper byte input active low. -upper byte (d 8 to d 15 ) is selected for read/write / erase function of ?sh memory cards. reg attribute memory select input active low. -attribute memory is selected for read/write function of identi?ation data of ?sh memory cards. (nc or ?f data or attribute data.) oe output enable input active low. -output enable for ?sh memory cards. we write enable input active low. -write enable for ?sh memory cards. cd 1, cd 2 card detect output these pins detect if the card has been correctly inserted. both pins are tied to gnd internally. wp write protect output write controller for ?sh memory cards. this pin outputs the protect/non protect status of ?p switch? bvd1, bvd2 battery voltage detect output both pins are tied to v cc internally. reset hardware reset input the card may be reset by driving the reset pin to v il . r/b ready/busy output system can be detect the completion of program or erase operation. v cc power supply power supply voltage. (+5.0 v 5%) gnd ground system ground. nc non connection 34 68 1 35 front side back side fig. 1 - bottom view (connector side)
7 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n block diagram MB98A81063, mb98a81183, mb98a81273 and mb98a81373 *1: not available for MB98A81063. fig. 2.1 - block diagram gnd internal circuit internal circuit v cc v cc 10 k v cc 100 k 510 k d 0 to d 15 v cc wp switch ce1 ce2 reg wp oe address bvd1 bvd2 cd 1 (even byte) 4m flash chip x 1 (81063) 8m flash chip x 1 (81183) 16m flash chip x 1 (81273) 16m flash chip x 2 (81373) address i/o we oe ce attribute memory address i/o r/b reset we oe ce r/b*1 reset we oe ce (odd byte) 4m flash chip x 1 (81063) 8m flash chip x 1 (81183) 16m flash chip x 1 (81273) 16m flash chip x 2 (81373) address i/o r/b buffer i/o buffer decoder wp control
8 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n block diagram (continued) mb98a81473 and mb98a81573 fig. 2.2 - block diagram gnd internal circuit internal circuit control circuit v cc v cc 10 k v cc 100 k 510 k v cc wp switch ce1 ce 2 reg we wp oe reset r/b bvd1 bvd2 cd 1 cd 2 address i/o r/b reset we oe ce address i/o we oe ce attribute memory address i/o r/b reset we oe ce address (odd byte) 16m flash chip x 4 (81473) 16m flash chip x 8 (81573) (even byte) 16m flash chip x 4 (81473) 16m flash chip x 8 (81573) buffer i/o buffer decoder wp control d 0 to d 15
9 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n chip and sector decoding - chip can be selected with; ? 0 , a 22 , a 23 and a 24 for x8-bit mode no.1. ? 22 , a 23 , and a 24 for x8-bit mode no.2 and x16-bit mode. - sector per each chip can be selected with a 17 , a 18 , a 19 , a 20 and a 21 . program / erase chip decoding table note: h = v ih , l = v il , x = either v ih or v il *1: available for mb98a81373, 81473 and 81573 only. *2: available for mb98a81473 and 81573 only. *3: available for mb98a81573 only. bus organization ce 2ce 1a 24 *3 a 23 *2 a 22 *1 a 0 decode chips 8-bit bus hl l l l l chip 0 h chip 1 h l chip 2 h chip 3 h l l chip 4 h chip 5 h l chip 6 h chip 7 h l l l chip 8 h chip 9 h l chip 10 h chip 11 h l l chip 12 h chip 13 h l chip 14 h chip 15 lh l l l x chip 1 h chip 3 h l chip 5 h chip 7 h l l chip 9 h chip 11 h l chip 13 h chip 15 16-bit bus l l l l l x chip 0, chip 1 h chip 2, chip 3 h l chip 4, chip 5 h chip 6, chip 7 h l l chip 8, chip 9 h chip 10, chip 11 h l chip 12, chip 13 h chip 14, chip 15
10 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n chip and sector decoding (continued) erase sector decoding table *1: a 20 is not available for MB98A81063. MB98A81063 has 8 sectors. *2: a 21 is not available for MB98A81063 and mb98a81183. MB98A81063 has 8 sectors and mb98a81183 has 16 sectors. card chip / sector configuration a card chip con?uration for 32mb card sector con?uration for 2 chips *1: 4m flash chip for MB98A81063. 8m flash chip for mb98a81183. *2: sector 7 for MB98A81063. sector 15 for mb98a81183. sector address (sa) a 21 *2 a 20 *1 a 19 a 18 a 17 sector 31 11111 sector 30 11110 sector 29 11101 total 32 sectors*1*2 per 1 chip sector 2 00010 sector 1 0 0 0 0 1 sector 0 00000 d 15 d 8 d 7 d 0 upper byte lower byte even address byte odd address byte chip 1 (16m flash chip *1 ) chip 0 (16m flash chip *1 ) chip 15 chip 14 sector 31 *2 (64k 8 bits) sector 31 *2 (64k 8 bits) chip 13 chip 12 chip 11 chip 10 chip 9 chip 8 chip 7 chip 6 chip 5 chip 4 sector 2 (64k 8 bits) sector 2 (64k 8 bits) chip 3 chip 2 sector 1 (64k 8 bits) sector 1 (64k 8 bits) chip1 chip 0 sector 0 (64k 8 bits) sector 0 (64k 8 bits) x 16 bit mode x 8 bit mode no. 1
11 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n function descriptions 1. read mode the data in the common and attribute memory can be read with ?e =v il and ?e =v ih ? the address is selected with a 0 to a 24 . and ce 1 and ce 2 select output mode (x8/x16 output mode, see ?unction truth tables?). the following 1) and 2) are the descriptions for common memory read and attribute memory read mode. (1) common memory read - two modes of common memory read, reading the data in memory array and intelligent id are available. the card entered each read mode by writing ?ead memory/reset command or ?ntelligent id read command? the card automatically resets to the condition of common memory read mode upon initial power-up. (2) attribute memory read - the data on the attribute memory can be read with ?eg =v il ? ?e =v il and ?e =v ih ? - an address on attribute memory can be selected with a 0 to a 11 pin. and ce 1 and ce 2 select output mode. 2. standby mode -ce 1 and ce 2 at ? ih place the card in standby mode. d 0 to d 15 are placed in a high-z state independent of the status ?e ? ?e and ?eg ? 3. output disable mode - the outputs are disabled with oe and we at ? ih ? d 0 to d 15 are placed in high-z state. 4. write mode (1) common memory write - the card is in write mode with ?e =v ih and ?e and ce =v il ? - commands can be written at the write mode. see ?.command de?itions? - two types of the write mode, ?e control and ?e control are available. (2) attribute memory write - reg at l-level selects attribute memory and ?e =v ih ? ?e and ce =v il place it in write mode. two types of the write mode, ?e control and ?e control are available. - attribute memory is not controlled by writing commands. and attribute memory has the data polling function, which can detect whether the attribute memory status is in programming operation. when the read operation is executed at programming cycle, the opposite data is output from d 7 (i7 ), and the same data (o 7 ) as the written data is output from d 7 pin at the completion of programming operation. 5. command de?itions - user can select the card operation by writing the speci? address and data sequences into the command register. if incollect address and data are written or improper sequence is done, the card is reseted to read mode. see ?ommand definision table? 6. automated program capability - programming operation can swich the data from ? to ?? - the data is programmed on a byte-by-byte or word-by-word basis. - the card will automatically provide adequate internally generated programming pulses and verify the programmed cell margine by writing four bus cycle operation. the card returns to common memory read mode automatically after the programming is completed. - addresses are latched at falling edge of we or ce and data is latched at rising edge of we or ce . the fourth rising edge of we or ce on the command write cycle begins programming operation. - we can check whether a byte (word) programming operation is completed successfully by sequence ?g with r/b (for mb98a81183, mb98a8xx73), data polling or toggle bit function. see ?rite operation status? - any commands written to the chip during programming operation will be ignored.
12 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n function descriptions (continued) 7. automated chip erase capability - we can execute chip erase operation by 6 bus cycle operation. chip erase does not require the user to program the chip prior to erase. upon executing the erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timing during these operations. - the card returns to common memory read mode automatically after the chip erasing is completed. - whether or not chip erase operation is completed successfully can be checked by sequence ?g with r/b (for mb98a81183, 8xx73 only), data polling or toggle bit function. see ?rite operation status? - any commands written to the chip during programming operation will be ignored. 8. automated sector erase capability - we can execute the erase operation on any sectors by 6 bus cycle operation. - a time-out of 50 m s (typ.) from the rising edge of the last sector erase command will initiate the sector erase command(s). - multiple sectors in a chip can be erased concurrently. this sequence is followed with writes of 30h to addresses in other sectors desired to be concurrently erased. the time between writes 30h must be less than 50 m s, otherwise that command will not be accepted. any command other than sector erase or erase suspend during this time-out period will reset the chip to read mode. the automated sector erase begins after the 50 m s (typ.) time out from the rising edge of we pulse for the last sector erase command pulse. whether the sector erase window is still open can be monitored with d 3 and d 11 . - sector erase does not require the user to program the chip prior to erase. the chip automatically programs ? to all memory locations in the sector(s) prior to electrical erase. the system is not required to provide any controls or timing during these operations. - the card returns to common memory read mode automatically after the chip erasing is completed. - whether or not sector erase operation is completed successfully can be checked by sequence ?g with r/b , data polling or toggle bit function. the sequence ?g must be read from the address of the sector involved in erase operation. see ?rite operation status? 9. erase suspend - erase suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is possible for MB98A81063). this command is applicable only during the sector erase operation (including the sector erase time-out period after the sector erase commands 30h) and will be ignored if written during the chip erase or programming operation. writing this command during the time-out will result in immediate termination of the time-out period. the addresses are ?on? cares in wrinting the erase suspend or resume commands in the chip. - when the erase suspend command is written during a sector erase operation, the chip will enter the erase suspend read mode. user can read the data from other sectors than those in suspention. the read operation from sectors in suspention results d 2 /d 10 toggling for mb98a81183 and mb98a8xx73. user can program to non-busy sectors by writing program commands for mb98a81183 and mb98a8xx73. - a read from a sector being erase suspended may result in invalid data. 10. intelligent identi?r (id) read mode - each common memory can execute an intelligent identi?r operation, initiated by writing intelligent id command (90h). following the command write, a read cycle from address 00h retrieves the manufacture code, and a read cycle from address 01h returns the device code as follows. to terminate the operation, it is necessary to write read/reset command. 11. hardware reset (not applied for MB98A81063) - the card may be reset by driving the reset pin to v ih . the reset pin must be kept high (v ih ) for at least 500 ns. any operation in progress will be terminated and the card will be reset to the read mode 20 m s after the reset pin is driven high. if a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. - when the reset pin is high and the internal reset is complete, the card goes to standby mode and cannot be accessed. also, note that all the data output pins are high-z for the duration of the reset pulse. once the reset pin is taken low, the card requires 500 ns of wake up time until outputs are valid for read access. - if hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used.
13 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n function descriptions (continued) 12. data protection - the card has wp (write protect) switch for write lockout. - to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko. it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. - if v cc would be less than v lko during program/erase operation, the operation will stop. and after that, the operation will not resume even if v cc returns recommended voltage level. therefore, program command must be written again because the data on the address interrupted program operation is invalid. and regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. - noise pulses of less than 5 ns (typical) on oe , ce or we will not initiate a write cycle. n function truth table main memory function*1 notes: *1: h =v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect, np = non protect *2: l-level is output when wpsw = np. h-level is output when wpsw = p. *3: not available for MB98A81063. mode reset*3 reg ce 2ce 1a 0 oe we wp* 2 data input/output wp sw d 8 to d 15 d 0 to d 7 hardware reset h xxxxxxx high-z p or np standby l xhhxxxx high-z read (x8 no.1) h hl l lhx high-z d out (even byte) read (x8 no.1) h d out (odd byte) read (x8 no.2) l h x d out (odd byte) high-z read (x16) l d out write (x8 no.1) hl l hl l high-z d in (even byte) np output disable h high-z p write (x8 no.1) h l d in (odd byte) np output disable h high-z p write (x8 no.2) l h x l d in (odd byte) np output disable h high-z p write (x16) l ld in np output disable h high-z p output disable xxxxhhx high-z p or np
14 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n function truth table (continued) attribute memory function*1 notes: *1: h = v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect, np = non protect *2: l-level is output when wpsw = np. h-level is output when wpsw = p. *3: not available for MB98A81063. mode reset*3 reg ce 2ce 1a 0 oe we wp* 2 data input/output wp sw d 8 to d 15 d 0 to d 7 standby l xhhxxxx high-z p or np read (x8 no.1) l hl l lhx high-z d out read (x8 no.1) h h read (x8 no.2) l h xh high-z read (x16) l d out write (x8 no.1) hl l hl l high-z d in np output disable h high-z p write (x8 no.1) h l invalid d in np output disable h high-z p write (x8 no.2) l h x l invalid d in np output disable h high-z p write (x16) l l invalid d in d in np output disable h high-z p output disable xxxxhhx high-z p or np
15 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n command definition table command table for 8-bit mode notes: ca: chip address. (address in chip selected by a 0 , a 22 , a 23 and a 24 ) sa: sector address (address in 64 kb selected by a 0 , a 17 , a 18 , a 19 , a 20 , a 21 , a 22 , a 23 and a 24 ) pa: program address (address to be programmed) ra: read address (address to be read) ia: intelligent id read address (manufacture code 0000h, device code 0002h) pd: programming data rd: read data id: intelligent identi?r (id) code ccma1, ccma2: command adddress for chip erase scma1, scma2: command address for sector erase pcma1, pcma2: command address for program rcma1, rcma2: command address for read/reset icma1, icma2: command address for intelligent id read command bus cycle 1st bus write cycle 2nd bus write/read cycle 3rd bus write cycle 4th bus write/read cycle 5th bus write cycle 6th bus write cycle read/reset 1 2 write read ca f0h ra rd read/reset 2 4 write write write read rcma 1 aah rcma 2 55h rcma 1 f0h ra rd read intelli- gent id codes 4 write write write read icma1 aah icma2 55h icma1 90h ia id byte program 4 write write write write pcma 1 aah pcma2 55h pcma 1 a0h pa pd sector erase 6 write write write write write write scma 1 aah scma2 55h scma 1 80h scma1 aah scma 2 55h sa 30h chip erase 6 write write write write write write ccma 1 aah ccma 2 55h ccma 1 80h ccma 1 aah ccma 2 55h ccma 1 10h sector erase suspend 1 write ca b0h sector erase resume 1 write ca 30h see ?ommand address table for 8-bit mode in page 17.
16 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 command table for 16-bit mode*1 notes: ca: chip address. (address in chip selected by a 22 , a 23 and a 24 ) sa: sector address (address in 128 kb selected by a 17 , a 18 , a 19 , a 20 , a 21 , a 22 , a 23 and a 24 ) pa: program address (address to be programmed) ra: read address (address to be read) ia: intelligent id read address (manufacture code 0000h, device code 0001h) pd: programming data rd: read data id: intelligent identi?r (id) code ccma1, ccma2: command address for chip erase scma1, scma2: command address for sector erase pcma1, pcma2: command address for program rcma1, rcma2: command address for read/reset icma1, icma2: command address for intelligent id read *1: address number is not contained ? 0 ? command bus cycle 1st bus write cycle 2nd bus write/read cycle 3rd bus write cycle 4th bus write/read cycle 5th bus write cycle 6th bus write cycle read/reset 1 2 write read f0f0h ra rd read/reset 2 4 write write write read rcma 1 aaaa h rcma 2 5555h rcma 1 f0f0h ra rd read intelli- gent id codes 4 write write write read icma1 aaaa h icma2 5555h icma1 9090h ia id byte program 4 write write write write pcma 1 aaaa h pcma2 5555h pcma 1 a0a0 h pa pd sector erase 6 write write write write write write scma 1 aaaa h scma2 5555h scma 1 8080h scma1 aaaa h scma 2 5555h sa 3030h chip erase 6 write write write write write write ccma 1 aaaa h ccma 2 5555h ccma 1 8080h ccma 1 aaaa h ccma 2 5555h ccma 1 1010h sector erase suspend 1 write ca b0b0 h sector erase resume 1 write ca 3030h see ?ommand address table for 16-bit mode in page 17.
17 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n command definition table (continued) command address table for 8-bit mode command address table for 16-bit mode command address MB98A81063 mb98a81183 mb98a81273, 81373, 81473, 81573 ccma1 (ca and 000001h) or aaaah (ca and 000001h) or aaah ca ccma2 (ca and 000001h) or 5554h (ca and 000001h) or 554h ca scma1 (sa and 000001h) or aaaah (sa and 000001h) or aaah ca scma2 (sa and 000001h) or 5554h (sa and 000001h) or 554h ca pcma1 (pa and 000001h) or aaaah (pa and 000001h) or aaah ca pcma2 (pa and 000001h) or 5554h (pa and 000001h) or 554h ca rcma1 (ra and 000001h) or aaaah (ra and 000001h) or aaah ca rcma2 (ra and 000001h) or 5554h (ra and 000001h) or 554h ca icma1 (ia and 000001h) or aaaah (ia and 000001h) or aaah ca icma1 (ia and 000001h) or 5554h (ia and 000001h) or 554h ca command address MB98A81063 mb98a81183 mb98a81273, 81373, 81473, 81573 ccma1 5555h 555h ca ccma2 2aaah 2aah ca scma1 5555h 555h ca scma2 2aaah 2aah ca pcma1 5555h 555h ca pcma2 2aaah 2aah ca rcma1 5555h 555h ca rcma2 2aaah 2aah ca icma1 5555h 555h ca icma1 2aaah 2aah ca
18 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n write operation status hardware sequence flag table notes: (1): erase suspended sector (2): non-erase suspended sector *1. performing successive read operations from the erase-suspended sector will cause d 2 , d 10 to toggle. *2. performing successive read operations from any address will cause d 6 , d 14 to toggle. *3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic ? at the d 2 , d 10 bit. however, successive reads from the erase-suspended sector will cause d 2 , d 10 to toggle. *4. not applied for MB98A81063. d 7 , d 15 (data polling) the card features data polling as a method to indicate to the host that the program/erase operation are in progress or completed. during the program operation an attempt to read the program address will produce the compliment of the data last written to d 7 /d 15 . upon completion of the program operation, an attempt to read the program address will produce the true data last written to d 7 /d 15 . during the erase operation, an attempt to read the program address will produce a ? at the d 7 /d 15 output. upon completion of the erase operation an attempt to read the device will produce a ? at the d 7 /d 15 output. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. even if the device has completed the operation and d 7 /d 15 has a valid data, the data outputs on d 0 to d 6 /d 8 to d 14 may be still invalid. the valid data on d 0 to d 7 /d 8 to d 15 will be read on the successive read attempts. the data polling feature is only active during the programming operation, erase operation, sector erase time- out, erase suspend read mode and erase suspend program mode. d 6 , d 14 (toggle bit l) the card also features the ?oggle bit as a method to indicate to the host system that the program/erase operation are in progress or completed. during an program or erase cycle, successive attempts to read (oe or ce toggling) data from the card will result in d 6 /d 14 toggling between one and zero. once the program or erase cycle is completed, d 6 /d 14 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is also active during the sector time out. either ce or oe toggling will cause the d 6 /d 14 to toggle. status d 7 , d 15 d 6 , d 14 d 5 , d 13 d 3 , d 11 d 2 , d 10 *4 r/b *4 in progress programming d 7 , d 15 toggle 0010 erasing 0 toggle 0 1 toggle 0 erase suspend read (1)1101*11 (2) data data data data data 1 erase suspend*4 program d 7 , d 15 *2 0 1 *1, *3 0 exceeded time limits programming d 7 , d 15 toggle 1010 erasing 0 toggle 1 1 n/a 0 erase suspend*4 program d 7 , d 15 toggle 1 1 n/a 0
19 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 d 5 , d 13 (exceeded timing limits) d 5 /d 13 will indicate if the program or erase time has exceeded the speci?d limits (internal pulse count). under these conditions d 5 /d 13 will produce a ?? this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the card under this condition. if this failure condition occurs during sector erase operation, it speci?s that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. the chip must be reset to use other sectors. write the reset command sequence to the chip, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the chip. if this failure condition occurs during the chip erase operation, it speci?s that the entire chip is bad or combination of sectors are bad. if this failure condition occurs during the byte programming operation, it speci?s that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). the d 5 /d 13 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the card locks out and never completes the card operation. hence, the system never reads a valid data on d 7 /d 15 bit and d 6 /d 14 never stops toggling. once the card has exceeded timing limits, the d 5 /d 13 bit will indicate a ?? please note that this is not a device failure condition since the device was incorrectly used. d 3 , d 11 (sector erase timer) after the completion of the initial sector erase command sequence the sector erase time-out will begin. d 3 /d 11 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the card has been written with a valid erase command, d 3 /d 11 may be used to determine if the sector erase timer window is still open. if d 3 /d 11 is high (?? the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if d 3 /d 11 is low (??, the card will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of d 3 /d 11 prior to and following each subsequent sector erase command. if d 3 /d 11 were high on the second status check, the command may not have been accepted. refer to table : hardware sequence flags. d 2 , d 10 (toggle bit ll, not applied for MB98A81063) this toggle bit, along with d 6 , can be used to determine whether the card is in the erase operation or in erase suspend. successive reads from the erasing sector will cause d 2 to toggle during the erase operation. if the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause d 2 to toggle. when the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic ??at the d 2 bit. d 6 is different from d 2 in that d 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. r/b (ready/busy , not applied for MB98A81063) the card provides a r/b open-drain output pin as a way to indicate to the system that the program or erase operation are either in progress or has been completed. if the output is low, the card is busy with either a program or erase operation. if the card is placed in an erase suspend mode, the r/b output will be high. during programming, the r/b pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the r/b pin is driven low after the rising edge of the sixth we pulse. the r/b pin will indicate a busy condition during the reset pulse.
20 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart start set pa yes fig. 3 - program flowchart completed d a t a polling or toggle bit *1 set address write command write command write command write data (pa/pd) last address ? increment pa no *1 see fig. 7, 6, 9, 10. *2 see ?ommand definition table? notes: pd : program data pa : program address
21 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) start set ca no fig. 4 - chip erase flowchart completed d a t a polling or toggle bit *1 write command write command write command desired other increment ca yes *1 see fig. 7, 8, 9, 10. *2 see ?ommand definition table? note: ca : chip address write command write command write command set address
22 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) set sa no fig. 5 - sector erase flowchart completed d a t a polling or toggle bit *1 write command (scma1/aah or aaaah)*3 write command (scma2/55h or 5555h)*3 desired other sectors erase ? yes *1 see fig.7, 8, 9, 10. *2 possible for the sectors in a chip *3 see ?ommand definition table? note: sa : sector address set address scma1,scma2*3 write command (sa/30h or 3030h) *2 start write command (scma1/80h or 8080h)*3 write command (scma1/aah or aaaah)*3 write command (scma2/55h or 5555h)*3 write command (sa/30h or 3030h)
23 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) no fig. 6 - erase suspend flowchart finished ye s *1 detection whether suspend mode is valid can be done by data polling and r/b also. (MB98A81063 does not have r/b). *2 only read operation for MB98A81063. notes: ca: chip address sa: sector address ra: read address executing sector erase read data (sa)*1 toggle bit=toggle?*1 read or program*2 stop erase suspend mode? write command (ca/30h or 3030h) no ye s write command (ca/b0h or b0b0h)
24 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) timer start *1 no fig. 7 - d a t a polling flowchart: x8 bit mode no.1 ye s *1 user sets the time period referring to ?rogram and erase performances? *2 programva=pa chip eraseva=ca sector eraseva=sa start read (va) *2 d 7 =data? no ye s d 5 =1 or time-up? read (va) *2 d 7 =data? error completed ye s no
25 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) timer start *1 ye s fig. 8 - toggle bit flowchart: x8 bit mode no.1 no *1 user sets the time period referring to ?rogram and erase performances? *2 program va=pa chip erase va=ca sector eraseva=sa start read (va) *2 d 6 =toggle? no ye s d 5 =1 or time-up? read (va) *2 d 6 =toggle? error completed no ye s
26 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) timer start *1 no ye s *1 user sets the time period referring to ?rogram and erase performances? *2 program va=pa chip erase va=ca sector eraseva=sa notes: ef: error flag ef=0: operation completed ef=1: lower byte error ef=2: upper byte error ef=3: lower/upper byte error start read (va) *2 no ye s d 5 =1 or time-up? read (va) *2 ef=1 ye s no d 7 =data? d 7 =data? 1 no ye s read (va) *1 no ye s d 13 =1 or time-up? read (va) ef=ef+2 ye s no d 15 =data? d 15 =data? 1 ye s ef=0? error completed no ef=0 fig. 9 - d a t a polling flowchart: x16 bit mode
27 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program / erase flowchart (continued) timer start *1 ye s no *1 user sets the time period referring to ?rogram and erase performances? *2 program va=pa chip erase va=ca sector eraseva=sa notes: ef: error flag ef=0: operation completed ef=1: lower byte error ef=2: upper byte error ef=3: lower/upper byte error start read (va) *2 no ye s d 5 =1 or time-up? read (va) ef=1 no ye s d 6 =toggle? d 6 =toggle? 1 ye s no read (va) *1 no ye s d 13 =1 or time-up? read (va) ef=ef+2 no ye s d 14 =tog- d 14 =toggle? 1 ye s ef=0? error completed no ef=0 fig. 10 - toggle bit flowchart: x16 bit mode
28 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n recommended operating conditions n dc characteristics notes: *1 this value does not apply to ce 1, ce 2, we and reg . *2 this value does not apply to bvd1, bvd2, cd1 and cd2. *3 this value does not apply to bvd1 and bvd2. n capacitance (t a = 25 c, f = 1 mhz, v in = v i/o = gnd) notes: *1 this value does not apply to ce 1, ce 2, we , reg and reset. *2 this value does not apply to cd 1, cd 2, bvd1 and bvd2. parameter symbol min. typ. max. unit v cc supply voltage v cc 4.75 5.0 5.25 v ground gnd 0 v ambient temperature t a 055 c parameter test conditons symbol value unit min. typ. max. input leakage current *1 v cc = v cc max., v in = 0 v or v cc i li 1.0 20 m a output leakage current *2 v cc = v cc max., v in = 0 v or v cc i lo 1.0 20 m a standby current v cc = v cc max. ce 1, ce 2 = v cc v in = 0 v or v cc i sb1 0.5 1.7 ma v cc = v cc max., ce 1, ce 2 = v ih v in = v il or v ih i sb2 4.0 8.0 ma active read current v cc = v cc max., ce 1, ce 2 = v il cycle = 200 ns, i out = 0 ma i cc1 100 160 ma program current program in progress (x16 mode) i cc2 120 ma erase current erase in progress (x16 mode) i cc3 120 ma input low voltage v il ?.3 0.8 v input high voltage v ih 2.4 v cc +0.3 v output low voltage i ol = 3.2 ma, v cc = v cc min. v ol 0.4 v output high voltage *3 i oh = 2.0 ma, v cc = v cc min. v oh 3.8 v low v cc lock-out voltage common memory attribute memory v lko 3.2 3.7 3.8 4.2 v v parameter symbol min. max. unit input capacitance *1 c in 75 pf i/o capacitance *2 c i/o 50 pf
29 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac test conditions n program and erase performances main memory program / erase performance (MB98A81063) notes: *1 excludes system-level overhead. *2 excludes 00h programming prior to erasure. (mb98a81183) notes: *1 excludes system-level overhead. *2 excludes 00h programming prior to erasure. parameter min. typ. max. unit byte program time *1 16 1000 m s chip programming time *1 8.5 50 sec. sector erase time *2 1.5 30 sec. program/erase cycles 100,000 1,000,000 cycles parameter min. typ. max. unit byte program time *1 8 2000 m s chip programming time *1 8 25 sec. sector erase time *2 1 15 sec. program/erase cycles 100,000 1,000,000 cycles fig. 11 - ac test conditions input pulse levels: v ih = 2.6 v, v il = 0.6 v input pulse rise and fall times: 5 ns (transient between 0.8 v and 2.4 v) input: v il = 0.8 v, v ih = 2.4 v output: v ol = 0.8 v, v oh = 2.0 v output load +5 v r1 r2 c l d out (i/o) * including jig and stray capacitance all parameters except t clz , t olz , t chz , t ohz , t rclz , t rolz , t clz , t olz , t chz, tohz , t rclz , t rolz , t rchz and t rohz 1.8 k w r1 1.8 k w r2 990 w 990 w c l 100 pf 5 pf parameter measured load i load i i
30 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n program and erase performances (continued) (mb98a81273, 81373, 81473, 81573) notes: *1 excludes system-level overhead. *2 excludes 00h programming prior to erasure. attribute memory program performance n ac characteristics (recommended operating conditions unless otherwise noted.) main memory read cycle*1 notes: *1 rise/fall time < 5 ns. *2 transition is measured at the point of 500 mv from steady state voltage. this parameter is speci?d using load ll in fig. 11. *3 this parameter is speci?d from the rising edge of oe , ce 1 or ce 2, whichever occurs ?st. parameter min. typ. max. unit byte programming time *1 8 2000 m s chip programming time *1 16 50 sec. sector erase time *2 1 15 sec. program/erase cycles 100,000 1,000,000 cycles parameter min. typ. max. unit byte program time 1 ms number of program per byte 100,000 times parameter symbol min. max. unit read cycle time trc 150 ns card enable access time tce 150 ns address access time tacc 150 ns output enable access time toe 75 ns card enable to output in low-z*2 tclz 5 ns card disable to output in high-z*2 tchz 60 ns output enable to output in low-z*2 tolz 5 ns output disable to output in high-z*2 tohz 60 ns output hold from address, ce , or oe change *3 toh 5 ns ready time from reset trdy 20 ms
31 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) main memory program / erase cycle*1 *2 notes: *1 read timing parameters during program/erase operations are the same as those during read only operations. refer to ac characteristics for main memory read cycle. *2 rise/fall time 5 ns. *3 these do not include the preprogramming time. *4 not 100% tested. parameter symbol min. typ. max. unit write cycle time twc 150 ns address setup time tas 20 ns address hold time tah 20 ns data setup time tds 50 ns data hold time tdh 20 ns read recovery time (we control) tghwl 10 ns read recovery time (ce control) tghel 10 ns output enable hold time toeh 10 ns card enable setup time tcs 20 ns card enable hold time tch 0 ns write enable pulse width twp 80 ns write enable setup time tws 0 ns write enable hold time twh 0 ns card enable pulse width tcp 100 ns duration of byte program operation (/we control) twhwh1 8 m s duration of erase operation *3 (/we control) twhwh2 1 15 s duration of byte program operation (/ce control) teheh1 8 m s duration of erase operation *3 (/ce control) teheh2 1 15 s v cc setup time *4 tvcs 50 m s reset pulse width trp 500 ns busy delay time tbsy 100 ns
32 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac characteristics (continued) attribute memory read cycle *1 notes: *1 rise/fall time < 5 ns. *2 transition is measured at the point of 500 mv from steady state voltage. this parameter is speci?d using load ll in fig. 3. *3 this parameter is speci?d from the rising edge of oe , ce 1 or ce 2, whichever occurs ?st. attribute memory program cycle parameter symbol min. max. unit read cycle time trrc 250 ns address access time traa 250 ns card enable access time trce 250 ns output enable access time troe 125 ns output hold from address change troh 5 ns card enable to output low-z *2 trclz 5 ns output enable to output low-z *2 trolz 5 ns card enable to output high-z *2 trchz 60 ns output enable to output high-z *2*3 trohz 60 ns parameter symbol min. max. unit address setup time tras 20 ns card enable setup time trcs 0 ns output enable setup time toes 20 ns write pulse width trwp 100 1000 ns address hold time trah 50 ns data setup time trds 50 ns data hold time trdh 20 ns card enable hold time trch 0 ns output enable hold time troeh 20 ns program time trwr 1 ms
33 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram main / attribute memory read cycle timing diagram (we = v ih , reg = v ih )*1 notes: *1 the addresses and parameters in ( ) are applied for attribute memory access. *2 a0 = either v ih or v il . ce 1 = oe = v il , ce 2 = v ih : x 8-bit no.1 bus organization read cycle 1: a 0 to a 24 (a 0 to a 11 ) d 0 to d 7 previous data valid data valid v ih v il v oh v ol previous data valid data valid ce 1 = v ih , ce 2 = oe = v il : x 8-bit no.2 bus organization read cycle 2: a 1 to a 24 * 2 (a 1 to a 11 ) d 8 to d 15 or v ih v il v oh v ol :unde?ed ce 1 = ce 2 = oe = v il : x 16-bit bus organization t rc t acc (traa) t oh (troh) t rc t acc (traa) t oh (troh)
34 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main / attribute memory read cycle timing diagram (continued) (we = v ih , reg = v ih )*1 note: *1 the addresses and parameters in ( ) are applied for attribute memory access. oe ce 1 ce 2 = v ih : x 8-bit no.1 bus organization read cycle 3: a 0 to a 24 (a 0 to a 11 ) high-z data valid v ih v il v oh v ol :unde?ed v ih v il v ih v il d 0 to d 7 t olz t acc (traa) t ce t clz t ohz t chz t oe
35 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main / attribute memory read cycle timing diagram(continued)(we = v ih , reg = v ih )*1 notes: *1 the addresses and parameters in ( ) are applied for attribute memory access. *2 a 0 = either v ih or v il . high-z data valid d 8 to d 15 ce 1 = v ih : x 8-bit no.2 bus organization read cycle 4: a 1 to a 24 * 2 (a 1 to a 11 ) v ih v il v oh v ol v ih v il v ih v il ce 1 = ce 2 = v il : x 16-bit bus organization read cycle 5: :unde?ed d 0 to d 15 a 1 to a 24 *2 (a 1 to a 11 ) v ih v il v oh v ol v ih v il v ih v il t olz high-z data valid t olz oe ce 2 oe ce 1=ce 2 t acc (traa) t chz t ohz t ce t clz (trclz) t oe t ce t clz t chz t ohz t oe
36 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory program cycle timing diagram (we = controlled, reg = v ih ) notes: *1 see ?unction truth table? *2 pcma1/pcma2 = command address for program, pa = program address, pd = program data. see ?om- mand definition table? a 0 to a 24 *1 v ih v il v ih v il :unde?ed v ih v il v ih v il data *1 v ih / oh v il / ol v cc t as t ah pcma1 *2 pcma2 *2 pcma1 *2 pa *2 pa *2 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle data polling cycle aah (aaaah) 55h (5555h) a0h (a0a0h) pd *2 d 7 ,d 15 pd *2 data t oeh t whwh1 t wph t cs t ch t ghwl twp tds tvcs tdh oe we t bsy v oh v ol r/b ce *1 t wc t rc t rc
37 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory program cycle timing diagram (ce = controlled, reg = v ih ) notes: *1 see ?unction truth table? *2 pcma1/pcma2 = command address for program, pa = program address, pd = program data. see ?om- mand definition table? a 0 to a 24 *1 v ih v il v ih v il :unde?ed v ih v il v ih v il data *1 v ih / oh v il / ol v cc t as t ah pcma1 *2 pcma2 *2 pcma1 *2 pa *2 pa *2 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle data polling cycle aah (aaaah) 55h (5555h) a0h (a0a0h) pd *2 d 7 ,d 15 pd *2 data t oeh t eheh1 t cph t ws t wh t ghel tcp tds tvcs tdh oe we ce *1 t bsy r/b v oh v ol t wc t rc t rc
38 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory erase cycle timing diagram (we = controlled, reg = v ih ) notes: *1 see function truth table. *2 ccma1/ccma2 = command address for chip erase, scma1/scma2 = command address for sector erase, sa = sector address. see command definition table. a 0 to a 24 *1 v ih v il v ih v il :undetned v ih v il v ih v il data *1 v ih / oh v il / ol v cc t as t ah 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle aah (aaaah) 55h (5555h) 80h (8080h) t wph t cs t ch t ghwl twp tds tvcs tdh aah (aaaah) 55h (5555h) 10h/30h (1010h/3030h) 5th bus cycle 6th bus cycle oe we ce *1 t wc ccma1/ scma1 *2 ccma2/ scma2 *2 ccma1/ scma1 *2 ccma1/ scma1 *2 ccma2/ scma2 *2 ccma1/ sa *2
39 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory erase cycle timing diagram (ce = controlled, reg = v ih ) notes: *1 see function truth table. *2 ccma1/ccma2 = command address for chip erase, scma1/scma2 = command address for sector erase, sa = sector address. see command definition table. a 0 to a 24 *1 v ih v il v ih v il :undetned v ih v il v ih v il data *1 v ih / oh v il / ol v cc t as t ah 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle aah (aaaah) 55h (5555h) 80h (8080h) t cph t ws t wh t ghel tcp tds tvcs tdh aah (aaaah) 55h (5555h) 10h/30h (1010h/3030h) 5th bus cycle 6th bus cycle oe we ce *1 t wc ccma1/ scma1 *2 ccma2/ scma2 *2 ccma1/ scma1 *2 ccma1/ scma1 *2 ccma2/ scma2 *2 ccma1/ sa *2
40 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory d a t a polling cycle timing diagram (reg = v ih ) notes: *1 va = pa for programming cycle, va = sa for sector erase, va = ca for chip erase. *2 see function truth table. *3 teheh1, 2 for ce control. *4 program/erase operation is tnished. a 0 to a 24 *2 v ih v il v ih v il :undetned v ih v il v ih v il d 7 ,d 15 v ih / oh v il / ol d 0 to d 6 *2 d 8 to d 14 t chz command write cycle data polling read cycle va *1 d 7 ,d 15 d 7 ,d 15 d 7 ,d 15 valid data *2 t oe *4 v ih / oh v il / ol oe we ce *2 t ce t acc t wc t oeh t ohz t whwh1,2 (t eheh1,2 )*3 d 0 to d 6 , d 8 to d 14 valid data d 0 to d 6 , d 8 to d 14 invalid data d 0 to d 6 , d 8 to d 14
41 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n timing diagram (continued) main memory toggle bit timing diagram (reg = v ih ) notes: *1 va = pa for programming cycle, va = sa for sector erase, va = ca for chip erase. *2 see ?unction truth table? *3 program/erase operation is ?ished. *4 pd, 10h (1010h) or 30h (3030h) a 0 to a 24 *2 v ih v il v ih v il :unde?ed v ih v il v ih v il data *2 v ih / oh v il / ol command write cycle *4 d 6 ,d 14 toggle d 6 ,d 14 toggle d 6 ,d 14 stop toggling valid data t oe va *1 va *1 va *1 va *1 toggle bit read cycle *3 oe we ce *2 t rc t oeh
42 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) attribute memory write cycle timing diagram (we = controlled, reg = v il ) note: *1 data polling operation. a 0 to a 11 high-z t rcs v ih v il v ih v il : unde?ed v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 1 t roes t rdh t rah t roeh t rwr d 0 to d 7 high-z o 7 i7 oe we ce 1 ce 2 = v i h : x 8-bit no.1 bus organization write cycle 1:
43 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) attribute memory write cycle timing diagram (we = controlled, reg = v il ) notes: *1 inputs from d 8 to d 15 are not de?ed. *2 data polling operation. ce 1 = ce 2 : x 16-bit bus organization write cycle 2: a 1 to a 11 high-z t rcs v ih v il v ih v il : unde?ed v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d 7 * 2 t roes t rdh t rah t roeh t rwr d 0 to d 7 * 1 high-z o 7 i7 ce1 =ce2 oe we
44 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n ac characteristics (continued) (recommended operating conditions unless otherwise noted.) r/b timing diagram during program / erase operations (except for MB98A81063) reset timing diagram (except for MB98A81063) entire programming or erase operation r/b ce we t rsy t rp t rdy reset possible next operation
45 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n unique features for flash memory card 1. special monitoring pins wp switch wp (output) protect h non protect l (a) (b) v cc cd 1 cd 2 system side card side - fig. 13 - - fig. 12- 1.1 cd1, cd2: card detection pins cd 1 and cd 2 are to detect whether or not the card has been correctly inserted. (see fig. 12.) when the memory card has been correctly inserted, cd 1 and cd 2 are detected by the system. cd 1, cd 2 are tied to ground on the card side as shown in fig. 12. 1.2 wp: write protect pins this pin monitors the position of the write protect switch. as shown in fig. 13, the flash memory card has a write protect switch at the top of the card. to write to the card, the switch must be turned to the ?on protect position and the we pin low. and at that time, l-level is output on the wp pin. to prevent writing to the card, the switch must be turned to the ?rotect position. at that time, h-level is output on the wp pin. non protect flash memory card write protect switch v cc protect
46 MB98A81063-/81183-/81273-/81373-/81473-/81573- 15 n package dimensions c 1997 fujitsu limited k68005sc-5-2 "a" 1.600.05 (.063.002) 85.600.20(3.370.008) 10.50(.413) 10.50(.413) 2-r1.00(.039) 1.000.05 (.039.002) 1.000.05 (.039.002) 1.000.05 (.039.002) 3.300.10(.130.004) 1.270.10(.050.004)typ. 3.300.20(.130.008) details of "a" part 1pin 1.270.10 (.050.004) 41.91 ref (1.650) 54.000.10 (2.126.004) 14.50(.571) dimensions in mm(inches). connector base 68 pin, plastic memory card (crd-68p-m05)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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